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Freescale Semiconductor /MK61F15WS /DDR /CR10

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Interpret as CR10

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TFAW0RESERVED 0TCPD0TRPAB0RESERVED

Description

DDR Control Register 10

Fields

TFAW

Time FAW
RESERVED

Reserved
TCPD

Time Clock Enable to Precharge Delay
TRPAB

TRP All Bank
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data